1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a thin film transistor (hereinafter referred to as TFT) with a GOLD (abbreviated form of “gate-overlapped-LDD”) structure and a method of manufacturing the same. Note that the semiconductor device in this specification indicates semiconductor devices in general the circuit of which is configured by semiconductor devices including a TFT with a GOLD structure. For example, semiconductor display devices such as an active matrix liquid crystal display device and an organic EL (abbreviated form of “electro-luminescence”) display device are included in the category of the semiconductor device.
2. Description of the Related Art
In semiconductor display devices, such as an active matrix liquid crystal display device and an organic EL display device, the circuit of which is configured by TFTs on a transparent insulating substrate such as a glass substrate, a polycrystalline silicon TFT having a high field-effect mobility has attracted attention. A polycrystalline silicon film applied to the polycrystalline silicon TFT has a higher field-effect mobility of an electron or hole than a conventional amorphous silicon film, and thus has an advantage that integration of not only a pixel transistor but also a driver circuit as a peripheral circuit can be realized. Therefore, each company has been advancing the development of an active matrix semiconductor display device the circuit of which is configured by polycrystalline silicon TFTs.
In the polycrystalline silicon TFT, it has a high field-effect mobility, but on the other hand, there is observed deterioration phenomena such as lowering of the field-effect mobility or an ON current (current that flows in an ON state) and increase in an OFF current (current that flows in an OFF state) when the polycrystalline silicon TFT is continuously driven. These have been problems in terms of reliability. The deterioration phenomenon is called a hot carrier phenomenon, and is known to be caused by hot carriers generated due to a high electric field in the vicinity of a drain.
The hot carrier phenomenon is one first discovered in a MOS (abbreviated form of “metal oxide semiconductor”) transistor which is manufactured on a semiconductor substrate, and it has been found that the cause of the phenomenon is the high electric field in the vicinity of a drain. Various basic examinations have been made for measures against hot carriers. The MOS transistor with a design rule of 1.5 μm or less adopts an LDD (abbreviated form of “lightly doped drain”) structure. In the LDD structure, an n-type or p-type low concentration impurity region (n− region or p− region) is formed in a drain end portion by utilizing a gate side wall that is comprised of an insulating film, and a gradient is imparted to an impurity concentration of a drain junction, thereby relaxing an electric field concentration in the vicinity of a drain. Here, an n-type low concentration impurity region and an n-type high concentration impurity region are respectively called an n− region and an n+ region, and a p-type low concentration impurity region and a p-type high concentration impurity region are respectively called a p− region and a p+ region.
However, in the LDD structure, the resistance of the low concentration impurity region (n− region or p− region) is large while a drain withstand voltage is improved much compared with a single drain structure. Thus, the LDD structure has a defect that a drain current decreases. Further, there has been the problem of a deterioration mode peculiar to the LDD in which: a high electric field region exists just under the side wall; impact ionization becomes maximum there; hot electrons are implanted into the side wall; and thus, the low concentration impurity region (n− region or p− region) is depleted, and the resistance is further increased. The above-mentioned problem has been tangible along with the reduction of a channel length. Thus, as to the MOS transistor with a design rule of 0.5 μm or less, the GOLD structure is developed in which a low concentration impurity region (n− region or p− region) is formed so as to overlap with an end portion of a gate electrode as a structure for overcoming the above-mentioned problem, and the application of the structure to mass production has been advancing.
Under the above-mentioned background, as to the polycrystalline silicon TFT manufactured on a transparent insulating substrate such as a glass substrate as well, the development of the LDD structure or GOLD structure has been progressing with the purpose of relaxing a high electric field in the vicinity of a drain, similar to the MOS transistor. The LDD structure is such that an n-type or p-type low concentration impurity region (n− region or p− region) that functions as an electric field relaxation region is formed in a semiconductor layer comprised of a polycrystalline silicon film corresponding to the outside of a gate electrode, and a high concentration impurity region (n+ region or p+ region) with the same conductivity as a source region or drain region is formed outside thereof. The LDD structure concerned has an advantage that an OFF current is small and a disadvantage that a hot carrier suppression effect due to relaxation of an electric field in the vicinity of a drain is small. On the other hand, in the GOLD structure, a low concentration impurity region (n− region or p− region) is formed so as to overlap with an end portion of a gate electrode. Thus, the GOLD structure has an advantage that a hot carrier suppression effect is large and a disadvantage that an OFF current increases, in comparison with the LDD structure.
As described above, each of the LDD structure and the GOLD structure has good points and bad points. Thus, in the actual semiconductor display device, from the viewpoint of quality improvement of the semiconductor display device, there is examined the effective combination in circuit configuration of a low OFF current characteristic of the LDD structure and a high hot carrier resistance of the GOLD structure. Specifically, in the case of a pixel TFT in a pixel region, the gate structure is preferable in which importance is placed on reduction in an OFF current value rather than high reliability to a hot carrier, and thus, the LDD structure having a low OFF current characteristic is suitable. On the other hand, in the case of a peripheral circuit consisting of a driver circuit, the gate structure is preferable in which importance is placed on high reliability to a hot carrier rather than a low OFF current characteristic, and thus, the GOLD structure having high hot carrier resistance is suitable. Therefore, the recent semiconductor display device the circuit of which is configured by a polycrystalline silicon TFT has a tendency that a pixel TFT in a pixel region is comprised of an LDD structure TFT, and a peripheral circuit is comprised of a GOLD structure TFT.
Note that, as to a known example on an n-channel polycrystalline silicon GOLD structure TFT, the structure and basic characteristics of the n-channel GOLD structure TFT are disclosed in Mutsuko Hatano, Hajime Akimoto, and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p 523-526, 1997. In the structure of the GOLD structure TFT examined here, a gate electrode and a side wall for LDD are formed of polycrystalline silicon, an n-type low concentration impurity region (n− region) that functions as an electric filed relaxation region is formed in an active layer (formed of polycrystalline silicon) just under the side wall for LDD, and a high concentration impurity region (n+ region) with the same conductivity which functions as a source region or drain region is formed outside thereof. As to the basic characteristics, a large drain current is obtained together with relaxation of a drain electric field, and a large suppression effect against a drain-avalanche-hot-carrier is obtained in comparison with the general LDD structure TFT.
Further, as to another example on the GOLD structure TFT, there are disclosed in JP 7-202210A, “a thin film transistor with an LDD structure which is characterized in that a gate electrode takes a structure of two layers having different widths, the upper layer of which has a smaller width than that of the lower layer” and “a method of manufacturing a thin film transistor with an LDD structure which is characterized in that: there is formed a gate electrode with a structure of two layers having different widths, the upper layer of which has a smaller width than that of the lower layer; and then, ions are implanted in a region that serves as a source or a drain using the gate electrode as a mask”. In JP 7-202210A concerned, there is described that “an acceleration voltage and an ion implantation amount at the time of ion implantation are appropriately selected, whereby an n+ region (or p+ region) in a region with no gate electrode, an n-region (or p− region) in a region only with a layer of a gate electrode, and an intrinsic (state with no ion implantation) region in a region with two layers of a gate electrode are simultaneously formed at the time of ion implantation”. There is provided a structure in which an n− region (or p− region) that is an electric field relaxation region overlaps with an end portion of a gate electrode, and therefore, the invention relating to the GOLD structure TFT is substantially disclosed.
In JP 2001-281704A, there is disclosed a method of manufacturing a GOLD structure TFT, including forming a gate electrode with a laminate structure of two layers and performing a dry etching process consisting of a large number of process steps comprising taper etching and anisotropic etching.
In JP 7-226518A, there is disclosed the invention in which: a film formed of a material constituting a gate electrode is formed; a mask is formed on the film formed of a material constituting the gate electrode; side etching is performed to the film formed of a material constituting the gate electrode to form a gate electrode having a smaller width than that of the mask; and an impurity is introduced into a semiconductor film to form an LDD region.
The development of the GOLD structure TFT excellent in hot-carrier resistance is being progressed in out company as well, and the structure of a typical GOLD structure TFT is described below with reference to FIGS. 3A and 3B. FIG. 3A is a sectional view of a GOLD structure TFT only having the Lov region. FIG. 3B is a sectional view of a GOLD structure TFT having both an Lov region and an Loff region. Note that, in this specification, an electric field relaxation region that overlaps with a gate electrode is referred to as an Lov region, and an electric field relaxation region that does not overlap with a gate electrode is referred to as an Loff region.
In the structure of the GOLD structure TFT only having an Lov region (FIG. 3A), on a transparent insulating substrate 301, an island-like semiconductor layer 302, a gate insulating film 303, and a gate electrode 304 are laminated from the side closer to the substrate 301, and a source region 305 and a drain region 306 are formed in the island-like semiconductor layer 302 outside the gate electrode 304. The above GOLD structure TFT is characterized in that: the gate electrode 304 is constituted of a first-layer gate electrode 304a and a second-layer gate electrode 304b; the first-layer gate electrode 304a is formed longer in size in a channel direction than the second-layer gate electrode 304b; electric field relaxation regions, that is, Lov regions 307 are formed in the island-like semiconductor layer 302 corresponding to the regions of the first-layer gate electrode 304a which are exposed from the second-layer gate electrode 304b; and the source region 305 and the drain region 306 are formed in the island-like semiconductor layer 302 corresponding to the outside of the gate electrode 304.
In the GOLD structure TFT with the above structure, the Lov region 307 is an electric field relaxation region formed so as to overlap with an end portion of the first-layer gate electrode 304a, and consists of an n-type or p-type low concentration impurity region (n− region or p− region). The Lov region 307 has a concentration gradient the impurity concentration of which gradually increases toward the source region 305 or the drain region 306 which is an n-type or p-type high concentration impurity region (n+ region or p+ region), and has a characteristic that electric field concentration in a depletion layer in the vicinity of the drain region 306 is further effectively relaxed. The concentration gradient of the Lov region 307 is formed by a method including accelerating an n-type or p-type impurity element in an electric field and making the impurity element pass through a laminate film of the first-layer gate electrode 304a corresponding to the region that is exposed from the second-layer gate electrode 304b and the gate insulating film 303 to be implanted into the island-like semiconductor layer 302 (through-doping method). The formation of the concentration gradient arises from the fact that the first-layer gate electrode 304a (the gate insulating film 303 is irrelevant because it does not change in thickness) which is the upper layer film of the island-like semiconductor layer 302 becomes thinner toward the end portion in implanting the impurity to the island-like semiconductor layer 302 with the through-doping method. Note that, in this specification, a doping method in which an impurity is made to pass through a certain substance layer positioned as the upper layer of an object substance layer to be implanted thereto is referred to as “through-doping method” for the sake of convenience.
Further, in the structure of the GOLD structure TFT having both an Lov region and an Loff region (FIG. 3B), on a transparent insulating substrate 401, an island-like semiconductor layer 402, a gate insulating film 403, and a gate electrode 404 are laminated from the side closer to the substrate 401, and a source region 405 and a drain region 406 are formed in the island-like semiconductor layer 402 outside the gate electrode 404. The above GOLD structure TFT is characterized in that: the gate electrode 404 is constituted of a first-layer gate electrode 404a and a second-layer gate electrode 404b; the first-layer gate electrode 404a is formed longer in size in a channel direction than the second-layer gate electrode 404b; first electric field relaxation regions, that is, Lov regions 407 are formed in the island-like semiconductor layer 402 corresponding to the regions of the first-layer gate electrode 404a which are exposed from the second-layer gate electrode 404b; and second electric field relaxation regions, that is, Loff regions 408 and the source region 405 and the drain region 406 are formed in the island-like semiconductor layer 402 corresponding to the outside of the gate electrode 404 so as to be adjacent to each other from the side closer to the gate electrode 404.
In the GOLD structure TFT with the above structure, the Lov region 407 is the first electric field relaxation region formed so as to overlap with an end portion of the first-layer gate electrode 404a, and consists of an n-type or p-type low concentration impurity region (n−− region or p−− region). The Lov region 407 has a concentration gradient the impurity concentration of which gradually increases toward the Loff region 408. Further, the Loff region 408 is the second electric field relaxation region formed so as not to overlap with the first-layer gate electrode 404a, and consists of an n-type or p-type low concentration impurity region (n− region or p− region). The Loff region 408 has a concentration gradient the impurity concentration of which gradually increases toward the source region 405 or the drain region 406 which is an n-type or p-type high concentration impurity region (n+ region or p+ region). Note that the concentration gradient of the Lov region 407 arises from the fact that the first-layer gate electrode 404a (the gate insulating film 403 is irrelevant because it does not change in thickness) which is the upper layer film of the island-like semiconductor layer 402 becomes thinner toward the end portion in implanting the impurity to the island-like semiconductor layer 402 with the through-doping method. Similarly, the concentration gradient of the Loff region 408 arises from the fact that the gate insulating film 403 that is the upper layer film of the island-like semiconductor layer 402 becomes thinner away from the gate electrode 404.
By the way, the gate electrodes 304, 404 of the GOLD structure TFTs shown in FIGS. 3A and 3B are constituted of the first-layer gate electrodes 304a, 404a and the second-layer gate electrodes 304b, 404b, respectively. The first-layer gate electrodes 304a, 404a are formed longer in size in a channel direction than the second-layer gate electrodes 304b, 404b, respectively. Then, the region of each of the first-layer gate electrodes 304a, 404a which is exposed from each of the second-layer gate electrodes 304b, 404b has a thin tapered shape, and thus, has a thinner thickness toward the end portion. A dry etching method that utilizes high density plasma which is capable of independently controlling a plasma density and a bias voltage applied to a substrate is suitable for processing of the gate electrodes 304, 404 with the above structure. As a specific dry etching method, a dry etching method is known which utilizes a microwave or inductively-coupled-plasma (hereinafter abbreviated to ICP). However, our company employs a dry etching apparatus of an ICP system. This is because the ICP dry etching apparatus enables easy control of plasma, and thus, has an advantage that a larger-scale processing substrate can be easily realized.
In the case where the gate electrodes 304, 404 are processed using the ICP dry etching apparatus, it is necessary to perform a dry etching process consisting of a large number of process steps in combination of taper etching and anisotropic etching. Here, in one process step, an etching process is performed under predetermined etching conditions. Note that the etching conditions mentioned here indicate a chamber pressure, an ICP power density, a bias power density, and a flow ratio of gases constituting etching gas.
For example, in the dry etching step of the gate electrode 304 of the GOLD structure TFT only having an Lov region (see FIG. 3A), the dry etching process consisting of three steps is performed, and thus, a changeover of the etching gas needs to be performed twice. The changeover of the etching gas requires a time until the pressure of an etching chamber is stabilized at the time of the changeover, which leads to the problem of reduction in throughput of the dry etching step. Moreover, there is required the etching gas that is flown until the pressure of the etching chamber is stabilized. Thus, there is also the problem of rise of the process cost due to consumption amount increase of the etching gas. Furthermore, in addition to the above problems, the complication of the dry etching step leads to the process defect and the increase of the number of troubles, and also involves the problem of reduction of yield of a semiconductor device.
Note that the above problems are not limited to the manufacturing steps of the GOLD structure TFT, and are found in the manufacturing steps of the LDD structure TFT as well. This is because the gate electrode is processed through the same dry etching step in either the GOLD structure TFT or the LDD structure TFT.